1. Field of the Invention
This invention relates to a resistance change memory device.
2. Description of the Related Art
Recently, it is noticed that a resistance change memory (ReRAM) succeeds to a conventional flash memory. The resistance change memory stores a resistance value state as data, which is reversibly changed by applying voltage, current, heat and the like, in the recording layer. The resistance change memory is suitable for shrinking the cell size, and for constituting a cross-point cell array. In addition, it is easy to stack cell arrays.
It is known that a variable resistance element used in a ReRAM has two types of operation modes. One is a bipolar type. In this type of ReRAMs, a high resistance state and a low resistance state are selectively set by exchanging the polarity of applying voltage. The other is a unipolar type. In this type of ReRAMs, it is possible to selectively set a high resistance state and a low resistance state by controlling the voltage applying time without exchanging the polarity of the applying voltage (for example, refer to Y. Hosoi et al, “High Speed Unipolar Switching Resistance RAM (RRAM) Technology” IEEE International Electron Devices Meeting 2006, Technical Digest, P. 793-796).
In the unipolar type of ReRAMs with a cross-point type of cell array, two operations are settable in accordance with combinations of voltages and applying times thereof as follows: one is for obtaining a low resistance value state from a high resistance value state (i.e., set or write operation); and the other is for obtaining a high resistance value state from a low resistance value state (i.e., reset or erase operation). Therefore, it is difficult to make a cell be in a set operation mode and make another cell be in a reset operation mode simultaneously, within plural cells selected by a selected word line.
With respect to a ReRAM having a cross-point type of cell array, there has already been proposed such a write scheme that identical data are written in multiple bits as data pattern used for estimating the memory function (for example, refer to JP-A-2006-323924).